1. Field of the Invention
The present invention relates to semiconductor devices and systems incorporating same. More particularly, the invention relates to a method of controlling on-die terminations for semiconductor memory devices sharing one or more transmission line (e.g., address lines, command lines, and/or data lines).
This application claims the benefit of Korean Patent Application No. 10-2006-0054370, filed on Jun. 16, 2006, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
Within semiconductor systems, it is generally necessary to match the impedance of a transmission line with a corresponding termination impedance (e.g., a resistor) in order to prevent undesirable signal reflections. Such signal reflections act as noise on the signal line in relation to signals subsequently transmitted on the transmission line.
Figure (FIG.) 1 is a block diagram of a conventional semiconductor system. Referring to FIG. 1, a controller 100 is connected to first and second memory devices 200 and 300, which are assumed to be DRAMs for purposes of illustration. Controller 100 outputs a clock signal CLK, first and second chip select signals CS0 and CS1, a command signal CMD, a data input/output signal DQ, and a data strobe signal DQS. First DRAM 200 receives the clock signal CLK, the first chip select signal CS0, the command signal CMD, the data input/output signal DQ, and the data strobe signal DQS. Second DRAM 300 receives the clock signal CLK, the second chip select signal CS1, the command signal CMD, the data input/output signal DQ, and the data strobe signal DQS.
Controller 100 includes a first On-Die Termination (ODT) 110 connected to a DQ line 400. In this context, the term “on-die” has reference to one or more element(s) integrated into the semiconductor die of controller 100. First ODT 110 includes a first resistor R0 connected between a power supply voltage terminal VDD and DQ line 400. First resistor R0 is assumed to have a conventionally common resistance of 60Ω.
First DRAM 200 includes a second ODT 210 connected to DQ line 400. Second ODT 210 includes a second resistor R1 and a first switch SW1 connected in series between the power supply voltage terminal VDD and DQ line 400. Second resistor R1 is also assumed to have a resistance of 60Ω. First switch SW1 is turned ON in response to a first ODT signal ODT0. The first ODT signal ODT0 is generated by a write command applied to first DRAM 200.
Second DRAM 300 includes a third ODT 310 connected to DQ line 400. Third ODT 310 includes a third resistor R2 and a second switch SW2 connected in series between the power supply voltage terminal VDD and DQ line 400. Third resistor R2 is assumed to have a resistance of 60Ω. Second switch SW2 is turned ON in response to a second ODT signal ODT1. The second ODT signal ODT1 is generated by a write command applied to second DRAM 300.
FIG. 2 is a timing diagram illustrating the operation of the semiconductor system shown in FIG. 1. Referring to FIG. 2, the clock signal CLK is applied to the semiconductor system. The first chip select signal CS0 and a first write command WR0 supplied to first DRAM 200 are generated in response to a first clock pulse C0 (e.g., in the illustrated example, a first leading or rising clock edge). The second chip select signal CS1 and a second write command WR1 applied to second DRAM 300 are generated in response to a third clock pulse C2. Thereafter, sequential data bursts corresponding to a first data group—FDIN0 through FDIN3, and a second data group—SDIN0 through SDIN3 are generated in response to the rising and falling edges of the data strobe signal DSQ. The first data group FDIN0 through FDIN3 is written to first DRAM 200 and the second data group SDIN0 through SDIN3 is written to second DRAM 300.
The first ODT signal ODT0 is enabled (i.e., logically “high” in the illustrated example) during clock pulses C1, C2, C3 and C4 following the first write command WR0. When the first ODT signal ODT0 is enabled, first switch SW1 of second ODT 210 of first DRAM 200 is turned ON. Accordingly, it is expected that first resistor R0 will impedance match second resistor R1, thereby preventing signal reflections from DQ line 400 during the transmission of the first data group FDIN0 through FDIN3 to first DRAM 200.
The second ODT signal ODT1 is enabled during clocks pulses C3 through C6 following the second write command WR1. When the second ODT signal ODT1 is enabled, second switch SW2 of third ODT 310 of second DRAM 300 is turned ON. Accordingly, it is expected that first resistor R0 will impedance match third resistor R2, thereby preventing signal reflections from DQ line 400 during transmission of the second data group SDIN0 through SDIN3 to second DRAM 300.
However, during the interval in which both the first and second ODT signals ODT0 and ODT1 are enabled, (e.g., clock pulses C3 and C4 in the illustrated example), DQ line 400 is effectively connected by parallel to first and second DRAMs 200 and 300 and corresponding second and third resistors R1 and R2. Thus, during the overlapping transmission intervals and with the foregoing assumptions, DQ line 400 has an impedance of 30Ω. Accordingly, the transmission line impedance of DQ line 400 intended to be matched to the 60Ω first ODT 110 in controller 100 is actually 30Ω. Thus, an impedance mismatch occurs during the transmission overlap interval. Continuing with the illustrated example, the data transmitted during data intervals FDIN2 and FDIN3 within the first data group and data transmitted during the data interval SDIN0 within the second data group can not be considered stable or reliably written to first and second DRAMs 200 and 300 via shared DQ line 400 due to the presence of signal reflections on the line.